module portbreg
	(clock, resetn, init, load, INIT, DATA, Q);
input			clock, resetn;
input			init, load;
input	[15:0]	INIT, DATA;
output	[15:0]	Q;

reg		[15:0]	Q;

always @(posedge clock or negedge resetn)
begin
	if (!resetn) Q <= 16'b0;
	else if (init) Q <= INIT;
	else if (load) Q <= DATA;
end

endmodule